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Disambiguation of "Girard, Patrick"

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Timing-aware ATPG for critical paths with multiple TSVs.

, , , , , and . DDECS, page 116-121. IEEE Computer Society, (2014)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Patrick Gralka University of Stuttgart

Patrick Maisenhölder University of Stuttgart

Patrick Lerge University of Stuttgart

Patrick Hippold University of Stuttgart

Patrick Mesmer University of Stuttgart

 

Other publications of authors with the same name

Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives., , , , and . PATMOS, volume 3728 of Lecture Notes in Computer Science, page 540-549. Springer, (2005)Agent-Based Architecture for Interactive System Design: Current Approaches, Perspectives and Evaluation., , , , , and . HCI (1), volume 5610 of Lecture Notes in Computer Science, page 624-633. Springer, (2009)Logical dynamics of belief change in the community., , and . Synthese, 191 (11): 2403-2431 (2014)Vérification de cohérence entre modèles de tâches et de dialogue en conception centrée-utilisateur., , , and . Ingénierie des Systèmes d'Information, 16 (5): 9-41 (2011)Delay-Fault Diagnosis by Critical-Path Tracing., , and . IEEE Design & Test of Computers, 9 (4): 27-32 (1992)A Layout-Aware Pattern Grading Procedure for Critical Paths Considering Power Supply Noise and Crosstalk., , and . J. Electronic Testing, 28 (2): 201-214 (2012)Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories., , , , , and . J. Electronic Testing, 21 (5): 551-561 (2005)A Ring Architecture Strategy for BIST Test Pattern Generation., , , and . J. Electronic Testing, 19 (3): 223-231 (2003)A Scan-BIST Structure to Test Delay Faults in Sequential Circuits., , , , and . J. Electronic Testing, 14 (1-2): 95-102 (1999)An advanced diagnostic method for delay faults in combinational faulty circuits., , and . J. Electronic Testing, 6 (3): 277-294 (1995)