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A signed hypergraph model of constrained via minimization.. Great Lakes Symposium on VLSI, page 159-166. IEEE, (1992)Parametric Equivalent Circuit Extraction for VLSI Structures., , and . VLSI-SOC, page 198-203. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)Fast-yet-accurate PVT simulation by combined direct and iterative methods., and . ICCAD, page 495-501. IEEE Computer Society, (2005)Bridging Circuits and Electromagnetics in a Curriculum Aimed at Microelectronic Analog and Microwave Simulation and Design., , , and . MSE, page 45-46. IEEE Computer Society, (2005)Distributed Event-Driven Simulation of VHDL-SPICE Mixed-Signal Circuits., and . ICCD, page 302-307. IEEE Computer Society, (2001)Exact Dichotomy-based Constrained Encodi., and . ICCD, page 426-431. IEEE Computer Society, (1996)IPRAIL - intellectual property reuse-based analog IC layout automation., , , and . Integration, 36 (4): 237-262 (2003)Code construction and FPGA implementation of a low-error-floor multi-rate low-density Parity-check code decoder., , and . IEEE Trans. on Circuits and Systems, 53-I (4): 892-904 (2006)Symmetry Detection for Automatic Analog-Layout Recycling., and . ASP-DAC, page 5-8. IEEE Computer Society, (1999)Hierarchical Multi-Dimensional Table Lookup for Model Compiler Based Circuit Simulation., and . DATE, page 1310-1315. IEEE Computer Society, (2004)