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Introduction to the January Special Issue on the 2015 IEEE International Solid-State Circuits Conference.

, , , , and . J. Solid-State Circuits, 51 (1): 3-7 (2016)

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3.6GHz 16-core SPARC SoC processor in 28nm., , , , , , , , , and 9 other author(s). ISSCC, page 48-49. IEEE, (2013)The Next Generation 64b SPARC Core in a T4 SoC Processor., , , , , , , , , and 7 other author(s). J. Solid-State Circuits, 48 (1): 82-90 (2013)A 40nm 16-core 128-thread CMT SPARC SoC processor., , , , , , , , , and 3 other author(s). ISSCC, page 98-99. IEEE, (2010)Bandwidth and power management of glueless 8-socket SPARC T5 system., , , and . ISSCC, page 58-59. IEEE, (2013)Session 4 overview: Processors: High-performance digital subcommittee., and . ISSCC, page 68-69. IEEE, (2015)The next-generation 64b SPARC core in a T4 SoC processor., , , , , , , , , and 5 other author(s). ISSCC, page 60-62. IEEE, (2012)The UltraSPARC T1 Processor: CMT Reliability., , and . CICC, page 555-562. IEEE, (2006)A dual-core 64b ultraSPARC microprocessor for dense server applications., , , , and . DAC, page 673-677. ACM, (2004)A 40 nm 16-Core 128-Thread SPARC SoC Processor., , , , , , , , , and 2 other author(s). J. Solid-State Circuits, 46 (1): 131-144 (2011)4.3 Fine-grained adaptive power management of the SPARC M7 processor., , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)