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K-Ways Partitioning of Polyhedral Process Networks: A Multi-level Approach., , , and . IPDPS Workshops, page 182-189. IEEE Computer Society, (2015)Runtime adaptation on dataflow HPC platforms., , , , , and . AHS, page 84-91. IEEE, (2013)Relocation-Aware Floorplanning for Partially-Reconfigurable FPGA-Based Systems., , , , and . IPDPS Workshops, page 97-104. IEEE Computer Society, (2015)Explicitly isolating data and computation in high level synthesis: the role of polyhedral framework., , , and . ReConFig, page 1-6. IEEE, (2015)A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops., , , , , and . ICCAD, page 77. ACM, (2016)On how to efficiently accelerate brain network analysis on FPGA-based computing system., , , , , and . ReConFig, page 1-6. IEEE, (2015)A Flexible Interconnection Structure for Reconfigurable FPGA Dataflow Applications., , , , , and . IPDPS Workshops, page 192-201. IEEE, (2013)An Enhanced Relocation Manager to Speedup Core Allocation in FPGA-based Reconfigurable Systems., , , , and . IPDPS Workshops, page 336-343. IEEE Computer Society, (2012)A Framework for Thermal and Performance Management., , , , , and . MAD, USENIX Association, (2012)A framework for effective exploitation of partial reconfiguration in dataflow computing., , , , , and . ReCoSoC, page 1-8. IEEE, (2013)