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Impact of Cell Failure on Reliable Cross-Point Resistive Memory Design.

C. Xu, D. Niu, Y. Zheng, S. Yu, and Y. Xie. ACM Trans. Design Autom. Electr. Syst., 20 (4): 63:1-63:21 (2015)

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Xu Chu

Chensheng Xu University of Stuttgart

Tongyu Xu University of Stuttgart

Yichen Xu University of Stuttgart

Dr. -Ing. Xu Chu University of Stuttgart

Other publications of authors with the same name

Memory and Storage System Design with Nonvolatile Memory Technologies.J. Zhao, C. Xu, P. Chi, and Y. Xie. IPSJ Trans. System LSI Design Methodology, (2015)Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach.C. Xu, Y. Zheng, D. Niu, X. Zhu, S. Kang, and Y. Xie. IEEE Trans. Multi-Scale Computing Systems, 1 (4): 195-206 (2015)NBWGuard: Realizing Network QoS for Kubernetes.C. Xu, K. Rajamani, and W. Felter. Middleware Industry, page 32-38. ACM, (2018)Pinatubo: a processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories.S. Li, C. Xu, Q. Zou, J. Zhao, Y. Lu, and Y. Xie. DAC, page 173:1-173:6. ACM, (2016)Optimizing the Topologies of Virtual Networks for Cloud-Based Big Data Processing.C. Xu, J. Yang, H. Yu, H. Lin, and H. Zhang. HPCC/CSS/ICESS, page 189-196. IEEE, (2014)Low power multi-level-cell resistive memory design with incomplete data mapping.D. Niu, Q. Zou, C. Xu, and Y. Xie. ICCD, page 131-137. IEEE Computer Society, (2013)Adaptive placement and migration policy for an STT-RAM-based hybrid cache.Z. Wang, D. Jiménez, C. Xu, G. Sun, and Y. Xie. HPCA, page 13-24. IEEE Computer Society, (2014)CREAM: A Concurrent-Refresh-Aware DRAM Memory architecture.T. Zhang, M. Poremba, C. Xu, G. Sun, and Y. Xie. HPCA, page 368-379. IEEE Computer Society, (2014)Using multi-level cell STT-RAM for fast and energy-efficient local checkpointing.P. Chi, C. Xu, T. Zhang, X. Dong, and Y. Xie. ICCAD, page 301-308. IEEE, (2014)PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory.P. Chi, S. Li, C. Xu, T. Zhang, J. Zhao, Y. Liu, Y. Wang, and Y. Xie. ISCA, page 27-39. IEEE Computer Society, (2016)

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Disambiguation of "Xu, Cong"

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Impact of Cell Failure on Reliable Cross-Point Resistive Memory Design.

Please choose a person to relate this publication to

Xu Chu

Chensheng Xu University of Stuttgart

Tongyu Xu University of Stuttgart

Yichen Xu University of Stuttgart

Dr. -Ing. Xu Chu University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Xu, Cong"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Impact of Cell Failure on Reliable Cross-Point Resistive Memory Design.

Please choose a person to relate this publication to

Xu Chu

Chensheng Xu University of Stuttgart

Tongyu Xu University of Stuttgart

Yichen Xu University of Stuttgart

Dr. -Ing. Xu Chu University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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Impact of Cell Failure on Reliable Cross-Point Resistive Memory Design.