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Disambiguation of "Lahiri, Kanishka"

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Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms.

, , , and . DATE, page 728-733. European Design and Automation Association, Leuven, Belgium, (2006)

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Other publications of authors with the same name

Variation-Tolerant Dynamic Power Management at the System-Level., , , and . IEEE Trans. VLSI Syst., 17 (9): 1220-1232 (2009)Fast performance analysis of bus-based system-on-chip communication architectures., , and . ICCAD, page 566-573. IEEE Computer Society, (1999)Fast system-level power profiling for battery-efficient system design., , and . CODES, page 157-162. ACM, (2002)Communication architecture based power management for battery efficient system design., , and . DAC, page 691-696. ACM, (2002)Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models., , , and . VLSI Design, page 579-585. IEEE Computer Society, (2005)Automatic Power Modeling of Infrastructure IP for System-on-Chip Power Analysis., , and . VLSI Design, page 513-520. IEEE Computer Society, (2007)Efficient Exploration of the SoC Communication Architecture Design Space., , and . ICCAD, page 424-430. IEEE Computer Society, (2000)Battery-efficient architecture for an 802.11 MAC processor., , and . ICC, page 669-674. IEEE, (2002)Characterizing Large Dataset GPU Compute Workloads Targeting Systems with Die-Stacked Memory., , , and . HiPC, page 204-213. IEEE Computer Society, (2015)The LOTTERYBUS on-chip communication architecture., , and . IEEE Trans. VLSI Syst., 14 (6): 596-608 (2006)