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Disambiguation of "Ziaja, Thomas A."

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Automatic Generation and Validation of Memory Test Models for High Performance Microprocessors.

, , and . ICCD, page 526-529. IEEE Computer Society, (2001)

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A. Laukemann

A. Laukemann

A. Laukemann

A. Vo{\ss}

A. Afkari

 

Other publications of authors with the same name

A Scalable, Low Cost Design-for-Test Architecture for UltraSPARCTM Chip Multi-Processors., , , , and . ITC, page 726-735. IEEE Computer Society, (2002)Sparc T4: A Dynamically Threaded Server-on-a-Chip., , , , , , , , , and 3 other author(s). IEEE Micro, 32 (2): 8-19 (2012)Transition Test on UltraSPARC- T2 Microprocessor., , , , , , , , , and 4 other author(s). ITC, page 1-10. IEEE Computer Society, (2008)Boundary scan in board manufacturing., and . J. Electronic Testing, 5 (2-3): 263-268 (1994)Characterization and analysis of errors in circuit test., and . DFT, page 261-268. IEEE Computer Society, (1995)Comprehensive Modeling of VLSI Test., and . DFT, page 159-167. IEEE Computer Society, (1996)Efficient Array Characterization in the UltraSPARC T2., and . VTS, page 3-8. IEEE Computer Society, (2009)Automatic Generation and Validation of Memory Test Models for High Performance Microprocessors., , and . ICCD, page 526-529. IEEE Computer Society, (2001)Using LSSD to test modules at the board level.. ITC, page 163-170. IEEE Computer Society, (1999)Design for testability features of the SUN microsystems niagara2 CMP/CMT SPARC chip., , , , , and . ITC, page 1-8. IEEE Computer Society, (2007)