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Leveraging 3D Technologies for Hardware Security: Opportunities and Challenges.

, , , , , , and . ACM Great Lakes Symposium on VLSI, page 347-352. ACM, (2016)

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Nonvolatile memory allocation and hierarchy optimization for high-level synthesis., , , , and . ASP-DAC, page 166-171. IEEE, (2015)PaCC: A Parallel Compare and Compress Codec for Area Reduction in Nonvolatile Processors., , , , , , , , and . IEEE Trans. VLSI Syst., 22 (7): 1491-1505 (2014)Near-Data Acceleration of Privacy-Preserving Biomarker Search with 3D-Stacked Memory., , , , and . DATE, page 800-805. IEEE, (2019)Optimal partition with block-level parallelization in C-to-RTL synthesis for streaming applications., , , , , , and . ASP-DAC, page 225-230. IEEE, (2013)Cost-efficient 3D Integration to Hinder Reverse Engineering During and After Manufacturing., , , , and . AsianHOST, page 74-79. IEEE, (2018)Boosting Deep Neural Network Efficiency with Dual-Module Inference., , , , , , , , , and . ICML, volume 119 of Proceedings of Machine Learning Research, page 6205-6215. PMLR, (2020)Nonvolatile Processor Architecture Exploration for Energy-Harvesting Applications., , , , , , and . IEEE Micro, 35 (5): 32-40 (2015)Utilizing voltage-frequency islands in C-to-RTL synthesis for streaming applications., , , , and . DATE, page 992-995. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Architecture design with STT-RAM: Opportunities and challenges., , , , , and . ASP-DAC, page 109-114. IEEE, (2016)A C2RTL Framework Supporting Partition, Parallelization, and FIFO Sizing for Streaming Applications., , , , , , , and . ACM Trans. Design Autom. Electr. Syst., 21 (2): 19:1-19:32 (2016)