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Automatic parallelization of fine-grained meta-functions on a chip multiprocessor., and . CGO, page 130-140. IEEE Computer Society, (2011)Bulk Disambiguation of Speculative Threads in Multiprocessors., , , and . ISCA, page 227-238. IEEE Computer Society, (2006)Computing in 3D., , , , , , , , , and 2 other author(s). 3DIC, page TS6.1.1-TS6.1.2. IEEE, (2015)Energy-Efficient Thread-Level Speculation., , , , , , and . IEEE Micro, 26 (1): 80-91 (2006)HiRe: using hint & release to improve synchronization of speculative threads., , , , and . ICS, page 143-152. ACM, (2012)CAVA: Using checkpoint-assisted value prediction to hide L2 misses., , , , and . TACO, 3 (2): 182-208 (2006)SoftSig: software-exposed hardware signatures for code analysis and optimization., , , and . ASPLOS, page 145-156. ACM, (2008)Improving the effectiveness of searching for isomorphic chains in superword level parallelism., and . MICRO, page 718-729. ACM, (2017)3D-enabled customizable embedded computer (3DECC)., , , , , , , , , and 2 other author(s). 3DIC, page 1-3. IEEE, (2014)Efficiently exploiting memory level parallelism on asymmetric coupled cores in the dark silicon era., , and . TACO, 8 (4): 28:1-28:21 (2012)