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1-D Cell Generation With Printability Enhancement.

, , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (3): 419-432 (2013)

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NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs., , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 33 (12): 1914-1927 (2014)Effective Wire Models for X-Architecture Placement., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 27 (4): 654-658 (2008)MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 27 (9): 1621-1634 (2008)X-architecture placement based on effective wire models., , and . ISPD, page 87-94. ACM, (2007)SoC test scheduling using the B-tree based floorplanning technique., , and . ASP-DAC, page 1188-1191. ACM Press, (2005)MDP-trees: multi-domain macro placement for ultra large-scale mixed-size designs., , , and . ASP-DAC, page 557-562. ACM, (2019)An integrated nonlinear placement framework with congestion and porosity aware buffer planning., , and . DAC, page 702-707. ACM, (2008)Essential Issues in Analytical Placement Algorithms., , and . IPSJ Trans. System LSI Design Methodology, (2009)1-D Cell Generation With Printability Enhancement., , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (3): 419-432 (2013)A Novel Analog Physical Synthesis Methodology Integrating Existent Design Expertise., , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 34 (2): 199-212 (2015)