Author of the publication

Energy-Scalable 4KB LDPC Decoding Architecture for NAND-Flash-Based Storage Systems.

, , and . IEICE Transactions, 99-C (2): 293-301 (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Efficient Parallel Architecture for Linear Feedback Shift Registers., , , and . IEEE Trans. on Circuits and Systems, 62-II (11): 1068-1072 (2015)High-Throughput and Area-Efficient MIMO Symbol Detection Based on Modified Dijkstra's Search., and . IEEE Trans. on Circuits and Systems, 57-I (7): 1756-1766 (2010)Double-Binary Circular Turbo Decoding Based on Border Metric Encoding., and . IEEE Trans. on Circuits and Systems, 55-II (1): 79-83 (2008)Synthesis of Application Specific Instructions for Embedded DSP Software., , , , , and . IEEE Trans. Computers, 48 (6): 603-614 (1999)High performance memory mode control for HDTV decoders., , and . IEEE Trans. Consumer Electronics, 49 (4): 1348-1353 (2003)Efficient Tree-Traversal Strategy for Soft-Output MIMO Detection Based on Candidate-Set Reorganization., and . IEEE Communications Letters, 17 (9): 1758-1761 (2013)A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory., , , , and . J. Solid-State Circuits, 48 (10): 2531-2540 (2013)Time-Domain Joint Estimation of Fine Symbol Timing Offset and Integer Carrier Frequency Offset., and . VTC Spring, page 1186-1190. IEEE, (2008)Synthesis and Optimization of Interface Hardware between IP's Operating at Different Clock Frequencies., , , and . ICCD, page 519-524. IEEE Computer Society, (2000)Low-Power Parallel Chien Search Architecture Using a Two-Step Approach., , and . IEEE Trans. on Circuits and Systems, 63-II (3): 269-273 (2016)