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Disambiguation of "de Gyvez, José Pineda"

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Supervised learning based model for predicting variability-induced timing errors.

, , , , , and . NEWCAS, page 1-4. IEEE, (2015)

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Jithin Jose University of Stuttgart

Basil Jose University of Stuttgart

Jörg Desel

Das ist Informatik (Eds.) Springer, (2001)

Univ. -Prof. Dr. Gerd de Bruyn University of Stuttgart

Anda Degeratu University of Stuttgart

 

Other publications of authors with the same name

Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits., and . IEEE Trans. VLSI Syst., 20 (1): 42-51 (2012)Stochastic Analysis of Deep-Submicrometer CMOS Process for Reliable Circuits Designs., , , , , and . IEEE Trans. on Circuits and Systems, 58-I (1): 164-175 (2011)A capacitor cross-coupled common-gate low-noise amplifier., , , , , , and . IEEE Trans. on Circuits and Systems, 52-II (12): 875-879 (2005)Fuzzy-Controlled Voltage Scaling Based on Supply Current Tracking., and . IEEE Trans. Computers, 62 (12): 2397-2410 (2013)Standard cell library tuning for variability tolerant designs., , , and . DATE, page 1-6. European Design and Automation Association, (2014)Reducing energy consumption in microcontroller-based platforms with low design margin co-processors., , , , , , and . DATE, page 269-272. ACM, (2015)Built-in Current Sensor for ?IDDQ Testing of Deep Submicron Digital CMOS ICs., and . VTS, page 53-58. IEEE Computer Society, (2004)Testing and Diagnosis of Power Switches in SOCs., , and . European Test Symposium, page 145-150. IEEE Computer Society, (2006)VDD Ramp Testing for RF Circuits., , and . ITC, page 651-658. IEEE Computer Society, (2003)Resistance Characterization for Weak Open Defects., , and . IEEE Design & Test of Computers, 19 (5): 18-26 (2002)