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Load-store optimization for software pipelining.

, , and . SIGARCH Computer Architecture News, 28 (1): 3-10 (2000)

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On the effectiveness of register moves to minimise post-pass unrolling in software pipelined loops., , and . HPCS, page 551-558. IEEE, (2012)On the Optimality of Register Saturation.. ICPP Workshops, page 563-570. IEEE Computer Society, (2004)Post-pass periodic register allocation to minimise loop unrolling degree., , and . LCTES, page 141-150. ACM, (2008)Early Control of Register Pressure for Software Pipelined Loops., and . CC, volume 2622 of Lecture Notes in Computer Science, page 17-32. Springer, (2003)Optimal acyclic fine-grain scheduling with cache effects for embedded and real time systems.. CODES, page 159-164. ACM, (2001)Early Periodic Register Allocation on ILP Processors., and . Parallel Processing Letters, 14 (2): 287-313 (2004)Performance evaluation and analysis of thread pinning strategies on multi-core platforms: Case study of SPEC OMP applications on intel architectures., , and . HPCS, page 273-279. IEEE, (2011)Register Saturation in Superscalar and VLIW Codes.. CC, volume 2027 of Lecture Notes in Computer Science, page 213-228. Springer, (2001)Dynamic Thread Pinning for Phase-Based OpenMP Programs., , and . Euro-Par, volume 8097 of Lecture Notes in Computer Science, page 53-64. Springer, (2013)Register pressure in instruction level parallelism.. Versailles Saint-Quentin-en-Yvelines University, France, (2002)