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Modeling of a double-sampling switched-capacitor bandpass delta-sigma modulator for multi-standard applications., , , , and . ASICON, page 465-468. IEEE, (2011)A highly pipelined VLSI architecture for all modes and block sizes intra prediction in HEVC encoder., , , , and . ASICON, page 1-4. IEEE, (2013)A 2D mesh NoC with self-configurable and shared-FIFOs routers., , , , and . ASICON, page 1-4. IEEE, (2013)A fast multi-core virtual platform and its application on software development., , , , and . ASICON, page 1-4. IEEE, (2013)Subthreshold Level Shifter With Self-Controlled Current Limiter by Detecting Output Error., , , , and . IEEE Trans. on Circuits and Systems, 63-II (4): 346-350 (2016)A low power register file with asynchronously controlled read-isolation and software-directed write-discarding., , , , and . ISCAS, page 349-352. IEEE, (2013)A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array., , , , , , , , , and 4 other author(s). ISSCC, page 56-57. IEEE, (2013)An area-efficient architecture for stochastic LDPC decoder., , , , and . DSP, page 244-247. IEEE, (2015)A single-routing layered LDPC decoder for 10Gbase-T Ethernet in 130nm CMOS., , , , , and . ASP-DAC, page 565-566. IEEE, (2012)A 60mW baseband SoC for CMMB receiver., , , , and . ASP-DAC, page 479-480. IEEE, (2012)