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Automated design error debug using high-level decision diagrams and mutation operators., , , , , and . Microprocessors and Microsystems - Embedded Hardware Design, 37 (4-5): 505-513 (2013)PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams., , , and . J. Electronic Testing, 25 (6): 289-300 (2009)Automated minimization of concurrent online checkers for Network-on-Chips., , , , , and . ReCoSoC, page 1-8. IEEE, (2015)Hierarchical Identification of Untestable Faults in Sequential Circuits., , , and . DSD, page 668-671. IEEE Computer Society, (2007)Fault Diagnosis in Integrated Circuits with BIST., , , , and . DSD, page 604-610. IEEE Computer Society, (2007)Parallel X-fault simulation with critical path tracing technique., , , and . DATE, page 879-884. IEEE, (2010)Layout to Logic Defect Analysis for Hierarchical Test Generation., , , , and . DDECS, page 35-40. IEEE Computer Society, (2007)Extensible open-source framework for translating RTL VHDL IP cores to SystemC., , and . DDECS, page 112-115. IEEE Computer Society, (2013)SoCDep2: A framework for dependable task deployment on many-core systems under mixed-criticality constraints., , , , , and . ReCoSoC, page 1-6. IEEE, (2016)Evolutionary Approach to Test Generation for Functional BIST, , , , and . CoRR, (2010)