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Disambiguation of "Lee, Donghyuk"

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Improving DRAM performance by parallelizing refreshes with accesses.

, , , , , , and . HPCA, page 356-367. IEEE Computer Society, (2014)

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Moosung Lee University of Stuttgart

Dongwon Lee University of Stuttgart

Junghwa Lee University of Stuttgart

Ph. D. Benjamin Lee University of Stuttgart

Hyosang Lee University of Stuttgart

 

Other publications of authors with the same name

Tiered-latency DRAM: A low latency and low cost DRAM architecture., , , , , and . HPCA, page 615-626. IEEE Computer Society, (2013)Exploiting the DRAM Microarchitecture to Increase Memory-Level Parallelism., , , , and . CoRR, (2018)Reducing DRAM Refresh Overheads with Refresh-Access Parallelism., , , , , , and . CoRR, (2018)Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms., , , , , , , , , and . SIGMETRICS (Abstracts), page 52. ACM, (2017)Understanding Latency Variation in Modern DRAM Chips: Experimental Characterization, Analysis, and Optimization., , , , , , , , , and . SIGMETRICS, page 323-336. ACM, (2016)A case for exploiting subarray-level parallelism (SALP) in DRAM., , , , and . ISCA, page 368-379. IEEE Computer Society, (2012)A Case for Memory Content-Based Detection and Mitigation of Data-Dependent Failures in DRAM., , , , and . IEEE Comput. Archit. Lett., 16 (2): 88-93 (2017)Estimation of Color Matching Functions for Tiled LCDs based on Genetic Algorithm., , , , , , and . Color Imaging: Displaying, Processing, Hardcopy, and Applications, page 1-4. Ingenta, (2016)Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms., , , , , , , , , and . POMACS, 1 (1): 10:1-10:42 (2017)Accelerating read mapping with FastHASH., , , , , and . BMC Genomics, 14 (S-1): S13 (2013)