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SqueezeNext: Hardware-Aware Neural Network Design.

, , , , , , , and . CVPR Workshops, page 1638-1647. IEEE Computer Society, (2018)

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Efficient per-element distortion contribution analysis via Harmonic Balance adjoints., and . CICC, page 1-4. IEEE, (2014)Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs., , , , , , , , , and 1 other author(s). FPGA, page 23-32. ACM, (2019)Shallow Networks for High-Accuracy Road Object-Detection., , , , and . CoRR, (2016)SqueezeDet: Unified, Small, Low Power Fully Convolutional Neural Networks for Real-Time Object Detection for Autonomous Driving., , , and . CoRR, (2016)FBNet: Hardware-Aware Efficient ConvNet Design via Differentiable Neural Architecture Search., , , , , , , , , and . CoRR, (2018)ChamNet: Towards Efficient Network Design through Platform-Aware Model Adaptation., , , , , , , , , and 3 other author(s). CoRR, (2018)SqueezeDet: Unified, Small, Low Power Fully Convolutional Neural Networks for Real-Time Object Detection for Autonomous Driving., , , and . CVPR Workshops, page 446-454. IEEE Computer Society, (2017)Time-domain segmentation based massively parallel simulation for ADCs., , , and . DAC, page 139:1-139:6. ACM, (2013)Poster: MAPP: The Berkeley Model and Algorithm Prototyping Platform., , , and . ICSE (2), page 825-826. IEEE Computer Society, (2015)ISBN 978-1-4799-1934-5 (Vol. I + II ???).LATTE: Accelerating LiDAR Point Cloud Annotation via Sensor Fusion, One-Click Annotation, and Tracking., , , and . ITSC, page 265-272. IEEE, (2019)