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Disambiguation of "Cho, SeongHwan"

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Optical PCB interconnects, Niche or mainstream?

, , , and . ISSCC, page 516. IEEE, (2012)

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Hyeongrae Cho University of Stuttgart

Michel Choudalakis University of Stuttgart

Gretchen Chojnacki-Herbers University of Stuttgart

King Cho Wong University of Stuttgart

 

Other publications of authors with the same name

A Quadrature Modulation Transmitter Using Two Frequency Synthesizers., and . IEEE Trans. on Circuits and Systems, 54-II (10): 907-911 (2007)A Hybrid-Domain Two-Step Time-to-Digital Converter Using a Switch-Based Time-to-Voltage Converter and SAR ADC., , , , and . IEEE Trans. on Circuits and Systems, 62-II (7): 631-635 (2015)CMRR enhancement technique for IA using three IAs for bio-medical sensor applications., , and . APCCAS, page 248-251. IEEE, (2010)A Low Power Transmitter for Phase-Shift Keying Modulation Schemes., and . PIMRC, page 1-5. IEEE, (2006)A 27.8μW Biopotential Amplifier Tolerant to 30Vpp Common-Mode Interference for Two-Electrode ECG Recording in 0.18μm CMOS., and . ISSCC, page 366-368. IEEE, (2019)An On-Chip Thermal Monitoring System With a Temperature Sensing Area of 52 µm2 in 180-nm CMOS., , and . IEEE Trans. on Circuits and Systems, 66-II (10): 1638-1642 (2019)A Time-Domain High-Order MASH ΔΣ ADC Using Voltage-Controlled Gated-Ring Oscillator., , , and . IEEE Trans. on Circuits and Systems, 60-I (4): 856-866 (2013)A 148fsrms Integrated Noise 4 MHz Bandwidth Second-Order ΔΣ Time-to-Digital Converter With Gated Switched-Ring Oscillator., , and . IEEE Trans. on Circuits and Systems, 61-I (8): 2281-2289 (2014)A 9 bit, 1.12 ps Resolution 2.5 b/Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register., , and . J. Solid-State Circuits, 49 (4): 1007-1016 (2014)19.3 A 2.4GHz 1.5mW digital MDLL using pulse-width comparator and double injection technique in 28nm CMOS., , , , and . ISSCC, page 328-329. IEEE, (2016)