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Disambiguation of "Diniz, Cláudio Machado"

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Parallelization of Full Search Motion Estimation Algorithm for Parallel and Distributed Platforms.

, , , , , and . International Journal of Parallel Programming, 42 (2): 239-264 (2014)

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Other publications of authors with the same name

A Reconfigurable Hardware Architecture for Fractional Pixel Interpolation in High Efficiency Video Coding., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 34 (2): 238-251 (2015)A real time H.264/AVC intra frame prediction hardware architecture for HDTV 1080P video., , , , and . ICME, page 1138-1141. IEEE, (2009)Timing and interface communication analysis of H.264/AVC encoder using SystemC model., , , and . VLSI-SoC, page 235-240. IEEE, (2010)Improving Content-Aware Video Streaming in Congested Networks with In-Network Computing., , , , , and . CoRR, (2022)A deblocking filter hardware architecture for the high efficiency video coding standard., , , , and . DATE, page 1509-1514. ACM, (2015)A novel pruned-based algorithm for energy-efficient SATD operation in the HEVC coding., , , and . SBCCI, page 1-6. IEEE, (2016)Parallelization of Full Search Motion Estimation Algorithm for Parallel and Distributed Platforms., , , , , and . International Journal of Parallel Programming, 42 (2): 239-264 (2014)High-throughput interpolation hardware architecture with coarse-grained reconfigurable datapaths for HEVC., , , and . ICIP, page 2091-2095. IEEE, (2013)A Pipelined 8x8 2-D Forward DCT Hardware Architecture for H.264/AVC High Profile Encoder., , , , , and . PSIVT, volume 4872 of Lecture Notes in Computer Science, page 5-15. Springer, (2007)Enhancing a HEVC interpolation filter hardware architecture with efficient adder compressors., , , and . NEWCAS, page 1-4. IEEE, (2015)