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Disambiguation of "Reisis, Dionysios I."

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A scalable optically-switched datacenter network with multicasting.

, , , , , , , , and . EuCNC, page 265-270. IEEE, (2016)

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I. Steinwart

I. Dudic

Cheng-I Ho University of Stuttgart

D. Inkermann

Tobias Ilg University of Stuttgart

 

Other publications of authors with the same name

A configurable length, Fused Multiply-Add floating point unit for a VLIW processor., , and . SoCC, page 93-96. IEEE, (2009)Using high-level synthesis to build memory and datapath optimized DSP accelerators., , and . ICECS, page 714-717. IEEE, (2014)Fully Systolic FFT Architecture for Giga-sample Applications., , , , , and . Signal Processing Systems, 58 (3): 281-299 (2010)Design and Comparison of FFT VLSI Architectures for SoC Telecom Applications with Different Flexibility, Speed and Complexity Trade-Offs., , , , , and . CSSP, 31 (2): 627-649 (2012)Parallel Memory Accessing for FFT Architectures., , , and . Signal Processing Systems, 90 (11): 1593-1607 (2018)NEPHELE: An End-to-End Scalable and Dynamically Reconfigurable Optical Architecture for Application-Aware SDN Cloud Data Centers., , , , , , , , , and 10 other author(s). IEEE Communications Magazine, 56 (2): 178-188 (2018)PANDA: asymmetric passive optical network for xDSL and FTTH access., , , , , , , , , and 13 other author(s). Panhellenic Conference on Informatics, page 335-342. ACM, (2013)A VLSI architecture for minimizing the transmission power in OFDM transceivers., , , and . ICECS, page 308-311. IEEE, (2003)A High Performance VLSI FFT Architecture., , , , , and . ICECS, page 810-813. IEEE, (2006)A real-time H.264/AVC VLSI encoder architecture., , , , , , , and . J. Real-Time Image Processing, 3 (1-2): 43-59 (2008)