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A 0.33 nJ/bit IEEE802.15.6/Proprietary MICS/ISM Wireless Transceiver With Scalable Data Rate for Medical Implantable Applications.

, , , , , , , , , , , , , , , and . IEEE J. Biomedical and Health Informatics, 19 (3): 920-929 (2015)

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Radio channel characterization for 400 MHz implanted devices., , , , , , , and . WCNC, page 293-298. IEEE, (2014)A 32-bit 16-program-cycle nonvolatile memory for analog circuit calibration in a standard 0.18µm CMOS., and . IEICE Electronic Express, 9 (6): 477-483 (2012)Foreword.. IEICE Transactions, 100-C (6): 513-514 (2017)A 0.33 nJ/bit IEEE802.15.6/Proprietary MICS/ISM Wireless Transceiver With Scalable Data Rate for Medical Implantable Applications., , , , , , , , , and 6 other author(s). IEEE J. Biomedical and Health Informatics, 19 (3): 920-929 (2015)Design Optimization of a High-Speed, Area-Efficient and Low-Power Montgomery Modular Multiplier for RSA Algorithm., , , and . IEICE Transactions, 88-C (4): 576-581 (2005)A Passive UHF RF Identification CMOS Tag IC Using Ferroelectric RAM in 0.35-µm Technology., , , , , , , , , and . J. Solid-State Circuits, 42 (1): 101-110 (2007)Self-Dithered Digital Delta-Sigma Modulators for Fractional-N PLL., , and . IEICE Transactions, 94-C (6): 1065-1068 (2011)A 3.5mW 5µsec settling time dual-band fractional-N PLL synthesizer., and . IEICE Electronic Express, 9 (4): 307-313 (2012)An ultra-low-power RF transceiver with a 1.5-pJ/bit maximally-digital impulse-transmitter and an 89.5-μW super-regenerative RSSI., , , , , , , and . A-SSCC, page 265-268. IEEE, (2014)Loop Design Optimization of Fourth-Order Fractional-N PLL Frequency Synthesizers., , and . IEICE Transactions, 95-A (8): 1337-1346 (2012)