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Disambiguation of "Carusone, Anthony Chan"

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Editorial ISCAS 2006 Special Section on Analog Circuits and Systems.

, and . IEEE Trans. on Circuits and Systems, 54-I (1): 191-192 (2007)

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Dr. phil. Geoffrey Chanda University of Stuttgart

 

Other publications of authors with the same name

A 10Gb/s 4.1mW 2-IIR + 1-discrete-tap DFE in 28nm-LP CMOS., and . ESSCIRC, page 439-442. IEEE, (2014)Channel characterization using jitter measurements., , and . ISCAS, page 2666-2669. IEEE, (2013)A 30-GS/sec Track and Hold Amplifier in 0.13-μm CMOS Technology., , and . CICC, page 493-496. IEEE, (2006)Gain and equalization adaptation to optimize the vertical eye opening in a wireline receiver., and . CICC, page 1-4. IEEE, (2010)Multi-Gb/s Bit-by-Bit Receiver Architectures for 1-D Partial-Response Channels., and . IEEE Trans. on Circuits and Systems, 57-I (1): 270-279 (2010)A passive filter aided timing recovery scheme., and . ISCAS, page 3065-3068. IEEE, (2008)A comparison of equalizers for compensating polarization-mode dispersion in 40-Gb/s optical systems., and . ISCAS (2), page 1521-1524. IEEE, (2005)A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS., , , , , , , , , and 3 other author(s). ISSCC, page 482-484. IEEE, (2019)Edge-Based Adaptation for a 1 IIR + 1 Discrete-Time Tap DFE Converging in 5~µs., , and . J. Solid-State Circuits, 51 (12): 3192-3203 (2016)A 6.8mW 7.4Gb/s clock-forwarded receiver with up to 300MHz jitter tracking in 65nm CMOS., and . ISSCC, page 158-159. IEEE, (2010)