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VLSI Architecture for Robust Speech Recognition Systems and its Implementation on a Verification Platform.

, , , and . JRM, 17 (4): 447-455 (2005)

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Study of PAPR reduction using coded PTS in 8×8 MIMO-OFDM systems., , and . ISPACS, page 363-368. IEEE, (2013)Development of an ASIP-based singular value decomposition processor in SVD-MIMO systems., , and . ISPACS, page 1-5. IEEE, (2011)Computational cost analysis and implementation of accelerated iterative shrinkage smoothing., , , and . APSIPA, page 1-4. IEEE, (2014)Variable wordlength soft-decision Viterbi decoder for power-efficient wireless LAN., , and . Integration, 45 (2): 132-140 (2012)Video wireless communication based on high speed 8×8 MIMO-OFDM system., , , , and . ISCCSP, page 586-589. IEEE, (2014)Region-of-interest based error resilient method for HEVC video transmission., , and . ISCIT, page 241-244. IEEE, (2015)Dynamic Buffer Status-Based Control for LTE-A Network With Underlay D2D Communication., and . IEEE Trans. Communications, 64 (3): 1342-1355 (2016)VLSI Implementation of a 4×4 MIMO-OFDM transceiver with an 80-MHz Channel Bandwidth., and . ISCAS, page 1743-1746. IEEE, (2009)A Performance-driven Approach to the High-level Synthesis of DSP Algorithms., , and . ISCAS, page 1658-1661. IEEE, (1993)An area and power efficient pipeline FFT processor for 8×8 MIMO-OFDM systems., , and . ISCAS, page 2705-2708. IEEE, (2011)