Author of the publication

A 0.7V 4.1mW 850Mbps/ch inductive-coupling transceiver with adaptive pulse width controller in 65nm CMOS.

, , , , and . RWS, page 71-74. IEEE, (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Hayashi, Isamu
add a person with the name Hayashi, Isamu
 

Other publications of authors with the same name

An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design., , , , , , , and . IEICE Transactions, 89-C (11): 1519-1525 (2006)A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS., , , , , , , , , and . J. Solid-State Circuits, 48 (11): 2671-2680 (2013)A 0.7V 4.1mW 850Mbps/ch inductive-coupling transceiver with adaptive pulse width controller in 65nm CMOS., , , , and . RWS, page 71-74. IEEE, (2012)0.5 V multi-phase digital controlled oscillator with smooth phase transition circuit., , , , and . APCCAS, page 232-235. IEEE, (2010)A 0.5V 6-bit scalable phase interpolator., , , , and . APCCAS, page 1019-1022. IEEE, (2010)A Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on SOI., , , , , and . CICC, page 429-432. IEEE, (2006)A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory., , , , , , , and . J. Solid-State Circuits, 42 (4): 853-861 (2007)A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs., , , , , and . J. Solid-State Circuits, 42 (11): 2611-2619 (2007)