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EIE: Efficient Inference Engine on Compressed Deep Neural Network.

, , , , , , and . ISCA, page 243-254. IEEE Computer Society, (2016)

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Transforming a linear algebra core to an FFT accelerator., , and . ASAP, page 175-184. IEEE Computer Society, (2013)A Systematic Approach to Blocking Convolutional Neural Networks., , , , , , , , and . CoRR, (2016)EIE: Efficient Inference Engine on Compressed Deep Neural Network., , , , , , and . ISCA, page 243-254. IEEE Computer Society, (2016)Algorithm, Architecture, and Floating-Point Unit Codesign of a Matrix Factorization Accelerator., , and . IEEE Trans. Computers, 63 (8): 1854-1867 (2014)On the Efficiency of Register File versus Broadcast Interconnect for Collective Communications in Data-Parallel Hardware Accelerators., , and . SBAC-PAD, page 19-26. IEEE Computer Society, (2012)Improving energy efficiency of DRAM by exploiting half page row access., , , , and . MICRO, page 1-12. IEEE Computer Society, (2016)Modeling Cache Effects at the Transaction Level., , and . IESS, volume 310 of IFIP Advances in Information and Communication Technology, page 89-101. Springer, (2009)Algorithm/Architecture Codesign of Low Power and High Performance Linear Algebra Compute Fabrics.. IPDPS Workshops, page 2214-2217. IEEE, (2013)Simulator calibration for accelerator-rich architecture studies., , , and . SAMOS, page 88-95. IEEE, (2016)Plasticine: A Reconfigurable Accelerator for Parallel Patterns., , , , , , , , and . IEEE Micro, 38 (3): 20-31 (2018)