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Challenges in the Formal Verification of Complete State-of-the-Art Processors.

, , and . ICCD, page 603-608. IEEE Computer Society, (2005)

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A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication., and . IEEE Symposium on Computer Arithmetic, page 225-232. IEEE Computer Society, (1999)Formal Verification of an Iterative Low-Power x86 Floating-Point Multiplier with Redundant Feedback. ACL2, volume 70 of EPTCS, page 70-83. (2011)(Modular) Effect Algebras are Equivalent to (Frobenius) Antispecial Algebras., and . QPL, volume 236 of EPTCS, page 145-160. (2016)Privacy Protocols., , and . Foundations of Security, Protocols, and Equational Reasoning, volume 11565 of Lecture Notes in Computer Science, page 167-191. Springer, (2019)High-Performance Multiplication Modulo 2n - 3.. ACSSC, page 130-134. IEEE, (2018)An FPGA Implementation of a Fully Verified Double Precision IEEE Floating-Point Adder., and . ASAP, page 83-88. IEEE Computer Society, (2007)Guest Editors' Introduction: Special Section on Computer Arithmetic., , and . IEEE Trans. Computers, 63 (8): 1852-1853 (2014)How to Half the Latency of IEEE Compliant Floating-Point Multiplication.. EUROMICRO, page 10329-10332. IEEE Computer Society, (1998)Delay-Optimized Implementation of IEEE Floating-Point Addition., and . IEEE Trans. Computers, 53 (2): 97-113 (2004)High-speed redundant reciprocal approximation.. Integration, 28 (1): 1-12 (1999)