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Control of Autonomic Parallelism Adaptation on Software Transactional Memory

, , , , and . International Conference on High Performance Computing & Simulation (HPCS 2016), page 180-187. Innsbruck, Austria, (July 2016)
DOI: 10.1109/HPCSim.2016.7568333

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Using Memory Access Traces to Map Threads and Data on Hierarchical Multi-core Platforms., , , , , and . IPDPS Workshops, page 551-558. IEEE, (2011)The mont-blanc prototype: an alternative approach for HPC systems., , , , , , , , , and 24 other author(s). SC, page 38. ACM, (2016)A Generic Component-Based Approach to MPSoC Observation., , , and . EUC, page 261-267. IEEE Computer Society, (2011)Autonomic Parallelism Adaptation for Software Transactional Memory, , , , and . Conférence d'informatique en Parallélisme, Architecture et Système (COMPAS), Lorient, France, (July 2016)Using the VI Architecture to Build Distributed, Multithreaded Runtime Systems: A Case Study., , , and . SAC (2), page 704-709. ACM, (2000)1-58113-240-9.Dynamic Thread Mapping Based on Machine Learning for Transactional Memory Applications., , , and . Euro-Par, volume 7484 of Lecture Notes in Computer Science, page 465-476. Springer, (2012)Using the Nanvix Operating System in Undergraduate Operating System Courses., , , , and . SBESC, page 193-198. IEEE Computer Society, (2017)An autonomic-computing approach on mapping threads to multi-cores for software transactional memory., , , , and . Concurrency and Computation: Practice and Experience, (2018)Para Miner: a generic pattern mining algorithm for multi-core architectures., , , and . Data Min. Knowl. Discov., 28 (3): 593-633 (2014)Improving the performance of actor model runtime environments on multicore and manycore platforms., , and . AGERE!@SPLASH, page 109-114. ACM, (2013)