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Block Cipher Speed and Energy Efficiency Records on the MSP430: System Design Trade-Offs for 16-Bit Embedded Applications.

B. Buhrow, P. Riemer, M. Shea, B. Gilbert, and E. Daniel. LATINCRYPT, volume 8895 of Lecture Notes in Computer Science, page 104-123. Springer, (2014)

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Erik Eppinger University of Stuttgart

Erik Hesselmeier University of Stuttgart

Erik Wimmer University of Stuttgart

Dr. Erik Poloni University of Stuttgart

S. Schumann

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A 20Gb/s SerDes transmitter with adjustable source impedance and 4-tap feed-forward equalization in 65nm bulk CMOS.R. Philpott, J. Humble, R. Kertis, K. Fritz, B. Gilbert, and E. Daniel. CICC, page 623-626. IEEE, (2008)Block Cipher Speed and Energy Efficiency Records on the MSP430: System Design Trade-Offs for 16-Bit Embedded Applications.B. Buhrow, P. Riemer, M. Shea, B. Gilbert, and E. Daniel. LATINCRYPT, volume 8895 of Lecture Notes in Computer Science, page 104-123. Springer, (2014)A Passive Differential Termination and Signal Sensing Device for High-Speed (40 Gb/s) Test Applications.C. Smutzer, P. Zabinski, B. Gilbert, and E. Daniel. IEEE Trans. Instrumentation and Measurement, 59 (7): 1775-1782 (2010)Characterization of semi-synthetic dataset for big-data semantic analysis.R. Techentin, D. Foti, S. Al-Saffar, P. Li, E. Daniel, B. Gilbert, and D. Holmes. HPEC, page 1-6. IEEE, (2014)Design of a Compact System Using a MEMS Accelerometer to Measure Body Posture and Ambulation.K. Bliley, D. Schwab, D. III, P. Kane, J. Levine, E. Daniel, and B. Gilbert. CBMS, page 335-340. IEEE Computer Society, (2006)A highly parallel AES-GCM core for authenticated encryption of 400 Gb/s network protocols.B. Buhrow, K. Fritz, B. Gilbert, and E. Daniel. ReConFig, page 1-7. IEEE, (2015)Simulated imaging of atherosclerotic & radiofrequency ablation lesions using phase subtraction.J. Jameson, D. III, B. Buhrow, E. Daniel, B. Gilbert, and C. Haider. EMBC, page 5630-5633. IEEE, (2015)Development of a Semi-synthetic Dataset as a Testbed for Big-Data Semantic Analytics.R. Techentin, D. Foti, P. Li, E. Daniel, B. Gilbert, D. Holmes, and S. Al-Saffar. ICSC, page 252-253. IEEE Computer Society, (2014)A 20 GS/s 5-Bit SiGe BiCMOS Dual-Nyquist Flash ADC With Sampling Capability up to 35 GS/s Featuring Offset Corrected Exclusive-Or Comparators.R. Kertis, J. Humble, M. Daun-Lindberg, R. Philpott, K. Fritz, D. Schwab, J. Prairie, B. Gilbert, and E. Daniel. J. Solid-State Circuits, 44 (9): 2295-2311 (2009)Introduction to the Special Section on the IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS 2008).W. Peatman, and E. Daniel. J. Solid-State Circuits, 44 (10): 2627-2628 (2009)