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A Content Adapted FPGA Memory Architecture with Pattern Recognition Capability for L1 Track Triggering in the LHC Environment.

, , , , and . FCCM, page 184-191. IEEE Computer Society, (2016)

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ALPS: A Methodology for Application-Level Communication Characterization of Parsec 2.1., , and . ICCS, volume 4 of Procedia Computer Science, page 2086-2095. Elsevier, (2011)A Content Adapted FPGA Memory Architecture with Pattern Recognition Capability for L1 Track Triggering in the LHC Environment., , , , and . FCCM, page 184-191. IEEE Computer Society, (2016)Evaluation of the Reconfiguration of the Data Acquisition System for 3D USCT., , , , , and . Int. J. Reconfig. Comp., (2011)Evaluation of performance and architectural efficiency of FPGAs and GPUs in the 40 and 28 nm generations for algorithms in 3D ultrasound computer tomography., , , and . Computers & Electrical Engineering, 40 (4): 1171-1185 (2014)A comprehensive comparison of GPU- and FPGA-based acceleration of reflection image reconstruction for 3D ultrasound computer tomography., , , , and . J. Real-Time Image Processing, 9 (1): 159-170 (2014)Acceleration of image reconstruction in 3D ultrasound computer tomography: An evaluation of CPU, GPU and FPGA computing., , , , , , and . DASIP, page 67-74. IEEE, (2011)RIVER architecture: Reconfigurable flow and fabric for parallel stream processing on FPGAs., , , , and . ReCoSoC, page 1-8. IEEE, (2012)RIVER: Reconfigurable Flow and Fabric for Real-Time Signal Processing on FPGAs., , and . TRETS, 7 (3): 24:1-24:16 (2014)A Content - Adapted FPGA Memory Architecture with Pattern Recognition Capability and Interval Compressing Technique., , , and . SoCC, page 206-212. IEEE, (2018)Online data reduction with a DSP-FPGA multiprocessor system., and . ISSPA, page 619-622. IEEE, (2001)