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Accelerating SPICE Model-Evaluation using FPGAs., and . FCCM, page 37-44. IEEE Computer Society, (2009)GraphStep: A System Architecture for Sparse-Graph Algorithms., , , , , , , , and . FCCM, page 143-151. IEEE Computer Society, (2006)Timing Fault Detection in FPGA-Based Circuits., , , and . FCCM, page 96-99. IEEE Computer Society, (2014)Design Patterns for Reconfigurable Computing., , , , , , , and . FCCM, page 13-23. IEEE Computer Society, (2004)GraphMMU: Memory Management Unit for Sparse Graph Accelerators., , , , and . IPDPS Workshops, page 113-120. IEEE Computer Society, (2015)An NoC Traffic Compiler for Efficient FPGA Implementation of Sparse Graph-Oriented Workloads., and . Int. J. Reconfig. Comp., (2011)On Data Forwarding in Deeply Pipelined Soft Processors., , and . FPGA, page 181-189. ACM, (2015)FastTrack: Exploiting Fast FPGA Wiring for Implementing NoC Shortcuts (Abstract Only)., and . FPGA, page 286. ACM, (2018)FPGA Acceleration of Irregular Iterative Computations using Criticality-Aware Dataflow Optimizations (Abstract Only)., and . FPGA, page 277. ACM, (2015)Hoplite: A Deflection-Routed Directional Torus NoC for FPGAs., and . TRETS, 10 (2): 14:1-14:24 (2017)