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Design space exploration of multi-task processing on space shared FPGAs: work-in-progress.

, , and . CODES+ISSS, page 10:1-10:2. ACM, (2019)

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Session TA5b: Computer arithmetic accelerators for signal processing.. ACSCC, page 980-982. IEEE, (2012)A Virtual Hardware Handler for RTR Systems., , , and . FCCM, page 262-263. IEEE Computer Society, (1999)How Resistant are Sboxes to Power Analysis Attacks?, , and . NTMS, page 1-6. IEEE, (2011)High Speed FPGA-Based Implementations of Delayed-LMS Filters., , , and . VLSI Signal Processing, 39 (1-2): 113-131 (2005)Implementation of fixed DSP functions using the reduced coefficient multiplier., , and . ICASSP, page 881-884. IEEE, (2001)Power efficient DSP datapath configuration methodology for FPGA., , and . FPL, page 515-518. IEEE, (2008)Soft IP core implementation of recursive least squares filter using only multplicative and additive operators., , and . FPL, page 597-600. IEEE, (2007)Highly efficient, limited range multipliers for LUT-based FPGA architectures., and . IEEE Trans. VLSI Syst., 12 (10): 1113-1118 (2004)Multidimensional DSP Core Synthesis for FPGA., , , and . VLSI Signal Processing, 43 (2-3): 207-221 (2006)NanoStreams: A Microserver Architecture for Real-Time Analytics on Fast Data Streams., , , , , , , , and . IEEE Trans. Multi-Scale Computing Systems, 4 (3): 396-409 (2018)