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Scan Attacks and Countermeasures in Presence of Scan Response Compactors.

, , , and . European Test Symposium, page 19-24. IEEE Computer Society, (2011)

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A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis., , and . J. Electronic Testing, 17 (3-4): 331-339 (2001)A Reliable Architecture for Parallel Implementations of the Advanced Encryption Standard., , , and . J. Electronic Testing, 25 (4-5): 269-278 (2009)Are advanced DfT structures sufficient for preventing scan-attacks?, , , and . VTS, page 246-251. IEEE Computer Society, (2012)Automatic Synthesis of BISTed Data Paths From High Level Specification., , and . EDAC-ETC-EUROASIC, page 591-598. IEEE Computer Society, (1994)A Reliable Architecture for the Advanced Encryption Standard., , , and . European Test Symposium, page 13-18. IEEE Computer Society, (2008)User-constrained test architecture design for modular SOC testing., , , , and . European Test Symposium, page 80-85. IEEE Computer Society, (2004)A smart test controller for scan chains in secure circuits., , , and . IOLTS, page 228-229. IEEE, (2013)Fitting ATE Channels with Scan Chains: a Comparison between a Test Data Compression Technique and Serial Loading of Scan Chains., , and . DELTA, page 295-300. IEEE Computer Society, (2006)3D DFT Challenges and Solutions., , , , , and . ISVLSI, page 603-608. IEEE Computer Society, (2015)A 3D IC BIST for pre-bond test of TSVs using ring oscillators., , , , and . NEWCAS, page 1-4. IEEE, (2013)