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Disambiguation of "Lewis, Dean L."

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An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth.

, , , and . HPCA, page 1-12. IEEE Computer Society, (2010)

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L. Ahlgrimm

Lambert Theisen University of Stuttgart

Annika Liebgott

Automated reference-free assessment of MR image quality using an active learning approach: Comparison of Support Vector Machine versus Deep Neural Network classification, , , , , , , and . Proceedings of the International Society for Magnetic Resonance in Medicine (ISMRM), Honolulu, Hawaii, USA, (April 2017)
Automated reference-free assessment of MR image quality using an active learning approach: Comparison of Support Vector Machine versus Deep Neural Network classification, , , , , , , and . Proceedings of the International Society for Magnetic Resonance in Medicine (ISMRM), Honolulu, Hawaii, USA, (April 2017)An easy-to-use image labeling platform for automatic Magnetic Resonance Image Quality Assessment, , , , , , and . Proceedings of the IEEE International Symposium on Biomedical Imaging (ISBI), Melbourne, Australia, (April 2017)Automated image quality assessment in whole-body MRI, , , , , , , , and . Proceedings of the Radiological Society of North America (RSNA), Chicago, USA, (November 2016)

Univ. -Prof. Dr. Remco Ingmar Leine University of Stuttgart

Christian León University of Stuttgart

 

Other publications of authors with the same name

Pre-bond testable low-power clock tree design for 3D stacked ICs., , , and . ICCAD, page 184-190. ACM, (2009)Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 30 (5): 732-745 (2011)An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth., , , and . HPCA, page 1-12. IEEE Computer Society, (2010)Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory., , , , , , , , , and 9 other author(s). CICC, page 1-4. IEEE, (2010)Architectural evaluation of 3D stacked RRAM caches., and . 3DIC, page 1-4. IEEE, (2009)Testing Circuit-Partitioned 3D IC Designs., and . ISVLSI, page 139-144. IEEE Computer Society, (2009)A scanisland based design enabling prebond testability in die-stacked microprocessors., and . ITC, page 1-8. IEEE Computer Society, (2007)Designing 3D test wrappers for pre-bond and post-bond test of 3D embedded cores., , , , and . ICCD, page 90-95. IEEE Computer Society, (2011)High Performance Non-blocking Switch Design in 3D Die-Stacking Technology., , and . ISVLSI, page 25-30. IEEE Computer Society, (2009)3D-MAPS: 3D Massively parallel processor with stacked memory., , , , , , , , , and 13 other author(s). ISSCC, page 188-190. IEEE, (2012)