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A Configurable Multi-Rail Power and I/O Pad Applied to Wafer-Scale Systems.

, , , and . IEEE Trans. on Circuits and Systems, 61-I (11): 3135-3144 (2014)

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Propagating analog signals through a fully digital network on an electronic system prototyping platform., , , and . ISCAS, page 1983-1986. IEEE, (2012)Digital signal propagation on a wafer-scale smart active programmable interconnect., , , , and . ICECS, page 1059-1062. IEEE, (2008)Thermo-mechanical analysis of a reconfigurable wafer-scale integrated circuit., , , , , , , and . ICECS, page 315-318. IEEE, (2010)Timing analysis speed-up using a hierarchical and a multimode approach., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 15 (2): 244-255 (1996)Defect diagnosis algorithms for a field programmable interconnect network embedded in a Very Large Area Integrated Circuit., , and . IOLTS, page 83-88. IEEE, (2015)Machine-learning framework for automatic netlist creation., , and . ISCAS, page 2865-2868. IEEE, (2011)An automated fault injection for evaluation of LUTs robustness in SRAM-based FPGAs., , , and . EWDTS, page 1-4. IEEE Computer Society, (2015)Towards an efficient SEU effects emulation on SRAM-based FPGAs., , , and . Microelectronics Reliability, (2016)Optimization of SEU emulation on SRAM FPGAs based on sensitiveness analysis., , , and . IOLTS, page 36-39. IEEE, (2015)Software rendering methods to display wafer scale integrated circuit dataset., , and . CCECE, page 1-4. IEEE, (2013)