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Embedded Transitive Closure Network for Runtime Deadlock Detection in Networks-on-Chip.

, , , , and . IEEE Trans. Parallel Distrib. Syst., 23 (7): 1205-1215 (2012)

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Advances in asynchronous logic: from principles to GALS & NoC, recent industry applications, and commercial CAD tools., , and . DATE, page 1715-1724. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Hybrid wire-surface wave architecture for one-to-many communication in networks-on-chip., , , , , and . DATE, page 1-4. European Design and Automation Association, (2014)Asynchronous design, Quo Vadis?. DDECS, page 3. IEEE Computer Society, (2010)Synthesis of Multiple Rail Phase Encoding Circuits., , and . ASYNC, page 95-104. IEEE Computer Society, (2009)A scalable FPGA-based design for field programmable large-scale ion channel simulations., , , , and . FPL, page 112-119. IEEE, (2012)Simulation Testing of a Real-Time Heuristic Scheduler with Automotive Benchmarks., , and . UKSim, page 424-429. IEEE, (2013)An elastic timer for wide dynamic working range., , , , and . NEWCAS, page 1-4. IEEE, (2015)Opportunistic Merge Element., , , and . ASYNC, page 116-123. IEEE Computer Society, (2015)Design of a DCO based on worst-case delay of a self-timed counter and a digitally controllable delay path., , , and . NEWCAS, page 1-4. IEEE, (2016)Speedup and Power Scaling Models for Heterogeneous Many-Core Systems., , , , , and . IEEE Trans. Multi-Scale Computing Systems, 4 (3): 436-449 (2018)