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Dual pillar spin-transfer torque MRAMs for low power applications., , , , , and . JETC, 9 (2): 14:1-14:17 (2013)Independently-Controlled-Gate FinFET 6T SRAM Cell Design for Leakage Current Reduction and Enhanced Read Access Speed., , , , , , , and . ISVLSI, page 296-301. IEEE Computer Society, (2014)Analysis of Functional Oxide based Selectors for Cross-Point Memories., , , and . IEEE Trans. on Circuits and Systems, 63-I (12): 2222-2235 (2016)ROBIN: Monolithic-3D SRAM for Enhanced Robustness with In-Memory Computation Support., , , , , , , , and . IEEE Trans. on Circuits and Systems, 66-I (7): 2533-2545 (2019)Improving FPGA Design with Monolithic 3D Integration Using High Dense Inter-Stack Via., , , , , , , , and . ISVLSI, page 128-133. IEEE Computer Society, (2017)High-performance low-energy STT MRAM based on balanced write scheme., , and . ISLPED, page 9-14. ACM, (2012)Device/circuit interactions at 22nm technology node., , and . DAC, page 97-102. ACM, (2009)Utilization of Negative-Capacitance FETs to Boost Analog Circuit Performances., , , , , and . IEEE Trans. VLSI Syst., 27 (12): 2855-2860 (2019)Digital Computation in Subthreshold Region for Ultralow-Power Operation: A Device-Circuit-Architecture Codesign Perspective., , and . Proceedings of the IEEE, 98 (2): 160-190 (2010)Low-Power Architecture for Epileptic Seizure Detection Based on Reduced Complexity DWT., , , , and . JETC, 8 (2): 10:1-10:14 (2012)