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Disambiguation of "Spallek, Rainer G."

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A New Level of Trusted Cloud Computing - Virtualized Reconfigurable Resources in a Security-First Architecture.

, , and . GI-Jahrestagung, volume P-275 of LNI, page 531-542. GI, (2017)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

G. Daiß

G. Wagner

apl. Prof. Dr. Rainer Bäuerle University of Stuttgart

Rainer Goutrié University of Stuttgart

Dr. Rainer Stöhr University of Stuttgart

 

Other publications of authors with the same name

RECAST - Design Space Exploration for Dynamic Reconfigurable Embedded Computing., , and . ESA/VLSI, page 130-135. CSREA Press, (2004)Generating the trace qualification configuration for MCDS from a high level language., and . DATE, page 1560-1563. IEEE, (2009)Formal Verification of a Reconfigurable Microprocessor., , , and . FPL, volume 1896 of Lecture Notes in Computer Science, page 781-784. Springer, (2000)Architecture Template and Design Flow to Support Applications Parallelism on Reconfigurable Platforms., and . FPL, volume 2778 of Lecture Notes in Computer Science, page 1119-1122. Springer, (2003)A Compiler-Oriented Architecture Description for Reconfigurable Systems., and . ARC, volume 3985 of Lecture Notes in Computer Science, page 443-448. Springer, (2006)Superblock compilation and other optimization techniques for a Java-based DPT machine emulator., and . VEE, page 33-40. ACM, (2013)Modellierung anwendungsspezifischer Hardware und deren Einbettung in die DBT-basierte Prozessor-Verhaltenssimulation., and . GI-Jahrestagung, volume P-275 of LNI, page 493-501. GI, (2017)Research and implementation of efficient parallel processing of big data at TELBE user facility., , , , , and . SummerSim, page 56:1-56:6. ACM, (2019)High-Level Architecture Modelling Assisting the Processor Platform Development, Debugging and Simulation., , and . MBMV, page 187-196. Universitätsbibliothek Berlin, Germany, (2009)Ready PCIe data streaming solutions for FPGAs., and . FPL, page 1-4. IEEE, (2014)