Author of the publication

Multi-Slot Main Memory System for Post DDR3.

, , and . IEEE Trans. on Circuits and Systems, 57-II (5): 334-338 (2010)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A Simplified Broadband Output Matching Technique for CMOS stacked Power Amplifiers., , , and . IEICE Transactions, 97-C (10): 938-940 (2014)A CMOS RF Power Detector Using an Improved Unbalanced Source Coupled Pair., , , and . IEICE Transactions, 91-C (12): 1969-1970 (2008)A Transconductor and Tunable Gm-C High-Pass Filter Linearization Technique Using Feedforward Gm3 Canceling., , and . IEEE Trans. on Circuits and Systems, 62-II (11): 1058-1062 (2015)A Wideband Noise-Cancelling Receiver Front-End Using a Linearized Transconductor., , and . IEICE Transactions, 100-C (3): 340-343 (2017)A 0.4-1.2GHz Reconfigurable CMOS Power Amplifier for 802.11ah/af Applications., and . IEICE Transactions, 102-C (1): 91-94 (2019)A Wall-Clutter Rejection Technique Using Two PLLs and a Phase Controller for Wall-Penetrating FMCW Radar., , , and . IEEE Geosci. Remote. Sens. Lett., 14 (4): 471-474 (2017)Challenges and directions of ultra low energy wireless sensor nodes for biosignal monitoring., , , , , and . ISCAS, page 986-989. IEEE, (2012)A Two-Stage Broadband Fully Integrated CMOS Linear Power Amplifier for LTE Applications., , , and . IEEE Trans. on Circuits and Systems, 63-II (6): 533-537 (2016)Architecture of a multi-slot main memory system for 3.2 Gbps operation., , , and . ISCAS, page 3857-3860. IEEE, (2010)A 0.1-1 GHz CMOS Variable Gain Amplifier Using Wideband Negative Capacitance., , , and . IEICE Transactions, 92-C (10): 1311-1314 (2009)