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Trace-Driven Steady-State Probability Estimation in FSMs with Application to Power Estimation.

, , and . DATE, page 774-779. IEEE Computer Society, (1998)

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Sequence compaction for power estimation: theory and practice., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 18 (7): 973-993 (1999)Information theoretic measures for power analysis logic design., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 15 (6): 599-610 (1996)A comprehensive and accurate latency model for Network-on-Chip performance analysis., , , , , and . ASP-DAC, page 323-328. IEEE, (2014)Sunflower : Full-System, Embedded Microarchitecture Evaluation., and . HiPEAC, volume 4367 of Lecture Notes in Computer Science, page 168-182. Springer, (2007)Regulatory network analysis acceleration with reconfigurable hardware., , , , , , and . EMBC, page 149-152. IEEE, (2011)Variation-adaptive feedback control for networks-on-chip with multiple clock domains., , and . DAC, page 614-619. ACM, (2008)Dynamic Fault-Tolerance and Metrics for Battery Powered, Failure-Prone Systems., and . ICCAD, page 633-640. IEEE Computer Society / ACM, (2003)Fault-Tolerant Techniques for Ambient Intelligent Distributed Systems., , , and . ICCAD, page 348-355. IEEE Computer Society / ACM, (2003)Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines., and . ISCA, page 310-321. IEEE Computer Society, (2005)Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors., and . ISCA, page 158-. IEEE Computer Society, (2002)