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Adaptive Selection of Cache Indexing Bits for Removing Conflict Misses.

, , , , and . IEEE Trans. Computers, 64 (6): 1534-1547 (2015)

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Distance-aware round-robin mapping for large NUCA caches., , , and . HiPC, page 79-88. IEEE Computer Society, (2009)An Efficient, Self-Contained, On-chip Directory: DIR1-SISD., , , and . PACT, page 317-330. IEEE Computer Society, (2015)Energy-Efficient Cache Coherence Protocols in Chip-Multiprocessors for Server Consolidation., , , and . ICPP, page 51-62. IEEE Computer Society, (2011)DASC-DIR: a low-overhead coherence directory for many-core processors., and . The Journal of Supercomputing, 71 (3): 781-807 (2015)Building Heterogeneous Unified Virtual Memories (UVMs) without the Overhead., , , and . ACM Trans. Archit. Code Optim., 13 (1): 1:1-1:22 (2016)Cache Miss Characterization in Hierarchical Large-Scale Cache-Coherent Systems., , , , and . ISPA, page 691-696. IEEE Computer Society, (2012)A Novel Lightweight Directory Architecture for Scalable Shared-Memory Multiprocessors., , and . Euro-Par, volume 3648 of Lecture Notes in Computer Science, page 582-591. Springer, (2005)Filter caching for free: the untapped potential of the store-buffer., , , and . ISCA, page 436-448. ACM, (2019)Non-Speculative Load-Load Reordering in TSO., , , and . ISCA, page 187-200. ACM, (2017)POSTER: Efficient Self-Invalidation/Self-Downgrade for Critical Sections with Relaxed Semantics., , , and . PACT, page 433-434. ACM, (2016)