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Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors .

, , and . DATE, page 10356-10363. IEEE Computer Society, (2003)

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Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors ., , and . DATE, page 10356-10363. IEEE Computer Society, (2003)Evaluation of algorithm optimizations for low-power Turbo-Decoder implementations., , , and . ICASSP, page 3101-3104. IEEE, (2002)Architecture-driven voltage scaling for high-throughput turbo-decoders., , and . J. Embedded Computing, 1 (3): 391-402 (2005)Optimized, highly parallel architectures for iterative decoding algorithms = Optimierte hochparallele Architekturen für iterative Decodierverfahren.. Kaiserslautern University of Technology, Germany, (2003)Low power implementation of a turbo-decoder on programmable architectures., , and . ASP-DAC, page 400-403. ACM, (2001)Concurrent interleaving architectures for high-throughput channel coding., , and . ICASSP (2), page 613-616. IEEE, (2003)Designing for Xilinx XC6200 FPGAs., , and . FPL, volume 1482 of Lecture Notes in Computer Science, page 29-38. Springer, (1998)A Scalable System Architecture for High-Throughput Turbo-Decoders., , , , and . VLSI Signal Processing, 39 (1-2): 63-77 (2005)Architecture-Driven Voltage Scaling for High-Throughput Turbo-Decoders., and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 379-388. Springer, (2003)Creative action teams: innovative opportunities for team work., , , and . SIGUCCS, page 160-164. ACM, (2005)