A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products.
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Disambiguation
The disambiguation is part of the PUMA genealogy project and is used to link unassigned publications to an existing person. You see the referenced publication of the author "Chang, T.", a list of already existing persons with the same author-name, and if available, other publications associated to them. Now you have the option to assign this publication to a person or create a new one.
