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Design of a Parallel Vector Access Unit for SDRAM Memory Systems., , , and . HPCA, page 39-48. IEEE Computer Society, (2000)REFS Keynote: "Requirements for Services: Does it Make Sense?".. COMPSAC (2), page 451-454. IEEE Computer Society, (2007)978-0-7695-2870-0.NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads., , , , , , , and . ISPASS, page 190-200. IEEE Computer Society, (2014)Comparing Implementations of Near-Data Computing with In-Memory MapReduce Workloads., , , , , , and . IEEE Micro, 34 (4): 44-52 (2014)CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study., , , , , , , , , and 1 other author(s). Low Power Networks-on-Chip, Springer, (2011)An Energy and Bandwidth Efficient Ray Tracing Architecture., , , , and . High Performance Graphics, page 121-128. ACM, (2013)HyperX: topology, routing, and packaging of efficient large-scale networks., , , , and . SC, ACM, (2009)Micro-pages: increasing DRAM efficiency with locality-aware data placement., , , , , and . ASPLOS, page 219-230. ACM, (2010)Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems., , , , and . ISCA, page 425-436. ACM, (2011)A Nanophotonic Interconnect for High-Performance Many-Core Computation., , , , , , , , , and 3 other author(s). Hot Interconnects, page 182-189. IEEE Computer Society, (2008)