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Disambiguation of "Ishizuka, Okihiko"

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VLSI Design of a Quaternary Multiplier with Direct Generation of Partial Products.

, , , , and . ISMVL, page 169-174. IEEE Computer Society, (1997)

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Other publications of authors with the same name

Learning Multiple-Valued Logic Networks Based on Back Propagation., , and . ISMVL, page 270-275. IEEE Computer Society, (1995)An immune network with interactions between B cells for pattern recognition., , , and . Systems and Computers in Japan, 32 (10): 31-41 (2001)VLSI Design of a Quaternary Multiplier with Direct Generation of Partial Products., , , , and . ISMVL, page 169-174. IEEE Computer Society, (1997)Low-Voltage, Low-Distortion and Rail-to-Rail CMOS Sample and Hold Circuit., , , and . IEICE Transactions, 88-A (10): 2696-2698 (2005)A Self-Calibrating A/D Converter Using T-Model Neural Network., , , and . ISCAS, page 533-536. IEEE, (1995)Application of Neuron-MOS to Current-Mode Multi-Valued Logic Circuits., , , and . ISMVL, page 128-133. IEEE Computer Society, (1998)Multi-Valued Logic Pass Gate Network Using Neuron-MOS Transistors., , , and . ISMVL, page 15-20. IEEE Computer Society, (2000)Algorithm and Implementation of a Learning Multiple-Valued Logic Network., , , and . ISMVL, page 202-207. IEEE Computer Society, (1993)A Learning Multiple-Valued Logic Network: Algebra, Algorithm, and Applications., and . IEEE Trans. Computers, 47 (2): 247-251 (1998)Realization of NMAX and NMIN Functions with Multi-Valued Voltage Comparators., , and . ISMVL, page 27-34. IEEE Computer Society, (2001)