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Incorporating performance and testability constraints during binding in high-level synthesis., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 15 (10): 1212-1225 (1996)Lower-bound performance estimation for the high-level synthesis scheduling problem., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 13 (4): 451-458 (1994)Estimating Performance Characteristics of Loop Transformations., and . ISCAS, page 249-252. IEEE, (1994)Estimating Lower-Bound Performance of Schedules Using a Relaxation Technique., and . ICCD, page 290-294. IEEE Computer Society, (1992)InSyn: integrated scheduling for DSP applications., and . IEEE Trans. Signal Processing, 43 (8): 1966-1977 (1995)Logo Retrieval in Document Images., and . Document Analysis Systems, page 135-139. IEEE Computer Society, (2012)RECALS II: a new list scheduling algorithm., and . ICASSP (2), page 461-464. IEEE Computer Society, (1994)Incorporating Testability Considerations in High-Level Systhesis., , and . FTCS, page 272-279. IEEE Computer Society, (1992)Optimal Allocation and Binding in High-Level Synthesis., , and . DAC, page 120-123. (1992)Module Selection for Pipelined Synthesis., , and . DAC, page 542-547. (1988)