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Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic.

, , , , , , and . ICCD, page 419-422. IEEE Computer Society, (2017)

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Efficient Communication Between the Embedded Processor and the Reconfigurable Logic on an FPGA., and . IEEE Trans. VLSI Syst., 16 (8): 1083-1090 (2008)New Performance Modeling Methods for Parallel Data Processing Applications., , , and . ACM Trans. Model. Comput. Simul., 29 (3): 15:1-15:24 (2019)A Methodology for Efficient Hardware Verification., and . Formal Methods in System Design, 5 (1/2): 95-117 (1994)PBS: proven Boolean simplification., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 13 (4): 459-470 (1994)Dynamo: a runtime partitioning system for FPGA-based HW/SW image processing systems., , and . J. Real-Time Image Processing, 2 (4): 179-190 (2007)Rothko: A Three-Dimensional FPGA., , , , , and . IEEE Design & Test of Computers, 15 (1): 16-23 (1998)Precision Modeling of Floating-Point Applications for Variable Bitwidth Computing., and . Engineering of Reconfigurable Systems and Algorithms, page 208-214. CSREA Press, (2003)Dynamo: A Runtime Partitioning System., , and . ERSA, page 145-154. CSREA Press, (2004)Enabling a Real-Time Solution for Neuron Detection with Reconfigurable Hardware., , , and . IEEE International Workshop on Rapid System Prototyping, page 128-134. IEEE Computer Society, (2005)Cross Component Optimization for Modern LTE Downlink Shared Channel Implementation., and . FCCM, page 225. IEEE Computer Society, (2018)