Author of the publication

Emulation-based hierarchical fault-injection framework for coarse-to-fine vulnerability analysis of hardware-accelerated approximate algorithms.

, , , , and . DATE, page 830-833. IEEE, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Multiple detection test generation with diversified fault partitioning paths., and . Microprocessors and Microsystems - Embedded Hardware Design, 38 (6): 585-597 (2014)On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation., , and . J. Electronic Testing, 24 (1-3): 203-222 (2008)A Non-Enumerative Technique for Measuring Path Correlation in Digital Circuits., , and . J. Electronic Testing, 28 (6): 843-856 (2012)A reconfigurable MPSoC-based QAM modulation architecture., , , , and . VLSI-SoC, page 137-142. IEEE, (2010)ATPG for Path Delay Faults without Path Enumeration., and . ISQED, page 384-389. IEEE Computer Society, (2001)Functions for Quality Transition Fault Tests., , and . ISQED, page 327-332. IEEE Computer Society, (2005)Optimal variable ordering in ZBDD-based path representations for directed acyclic graphs., and . ICCD, page 489-492. IEEE Computer Society, (2014)Tackling the complexity of exact path delay fault grading for path intensive circuits., and . ETS, page 1-2. IEEE, (2015)Exploiting Shared-Memory to Steer Scalability of Fault Simulation Using Multicore Systems., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 38 (8): 1466-1479 (2019)Guest Editorial: Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology., , and . IEEE Trans. Emerging Topics Comput., 6 (4): 447-449 (2018)