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Micro-architectural approach to the efficient employment of STTRAM cells in a microprocessor register file., , , and . IET Computers & Digital Techniques, 11 (1): 1-7 (2017)An Efficient Programming Skeleton for Clusters of Multi-Core Processors., , and . International Journal of Parallel Programming, 46 (6): 1094-1109 (2018)An Efficient Data Aggregation Method for Event-Driven WSNs: A Modeling and Evaluation Approach., , , and . Wireless Personal Communications, 84 (1): 745-764 (2015)An Efficient Method to Reliable Data Transmission in Network-on-Chips., , and . DSD, page 467-474. IEEE Computer Society, (2010)FasTest: A Concurrent Strategy to Test Components of 3D Network-on-Chips., , , and . MWSCAS, page 65-68. IEEE, (2019)Vulnerability modelling of crypto-chips against scan-based attacks., , and . IET Information Security, 12 (6): 543-550 (2018)Coding Last Level STT-RAM Cache for High Endurance and Low Power., , , and . IEEE Comput. Archit. Lett., 13 (2): 73-76 (2014)Comparative analytical performance evaluation of adaptivity in wormhole-switched hypercubes., and . Simulation Modelling Practice and Theory, 15 (4): 400-415 (2007)Performance/energy aware task migration algorithm for many-core chips., , and . IET Computers & Digital Techniques, 10 (4): 165-173 (2016)Fault-tolerant routing methodology for hypercube and cube-connected cycles interconnection networks., and . The Journal of Supercomputing, 73 (10): 4560-4579 (2017)