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Fast on-chip inductance simulation using a precorrected-FFT method.

, , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 22 (1): 49-66 (2003)

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Worst case clock skew under power supply variations., , , , , , and . Timing Issues in the Specification and Synthesis of Digital Systems, page 22-28. ACM, (2002)Fast on-chip inductance simulation using a precorrected-FFT method., , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 22 (1): 49-66 (2003)Fast Analysis and Optimization of Power/Ground Networks., , and . ICCAD, page 477-480. IEEE Computer Society, (2000)Inductance 101: Analysis and Design Issues., , , , and . DAC, page 329-334. ACM, (2001)On-chip inductance modeling., , , , and . ACM Great Lakes Symposium on VLSI, page 75-80. ACM, (2000)Inductance model and analysis methodology for high-speed on-chip interconnect., , , , and . IEEE Trans. VLSI Syst., 10 (6): 730-745 (2002)Table look-up based compact modeling for on-chip interconnect timing and noise analysis., , , , , , and . ISCAS (4), page 668-671. IEEE, (2003)A precorrected-FFT method for simulating on-chip inductance., , , , , , and . ICCAD, page 221-227. ACM / IEEE Computer Society, (2002)On-chip inductance modeling and analysis., , , , , and . DAC, page 63-68. ACM, (2000)Statistical delay computation considering spatial correlations., , , , , , and . ASP-DAC, page 271-276. ACM, (2003)