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Fine-Grained Parallel VLSI Synthesis for Commercial CAD on a Network of Workstations., , and . ICPP, page 421-430. IEEE Computer Society, (2000)A portable parallel algorithm for logic synthesis using transduction., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 13 (5): 566-580 (1994)Fine-Grained Processing Towards HL-LHC Computing in ATLAS., , , , , , , , , and 6 other author(s). eScience, page 338. IEEE Computer Society, (2018)Poster: PanDA: Next Generation Workload Management and Analysis System for Big Data., , , , , , , and . SC Companion, page 1523. IEEE Computer Society, (2012)Parallel algorithms for logic synthesis using the MIS approach., , , , and . IPPS, page 579-585. IEEE Computer Society, (1995)Logic Partitioning and Resynthesis for Testability., and . ITC, page 906-915. IEEE Computer Society, (1991)Failure Analysis for Full-Scan Circuits., and . ITC, page 636-645. IEEE Computer Society, (1995)Test methodology for embedded cores which protects intellectual property.. VTS, page 2-9. IEEE Computer Society, (1997)Accurate pre-layout estimation of standard cell characteristics., , and . DAC, page 208-211. ACM, (2004)Abstract: PanDA: Next Generation Workload Management and Analysis System for Big Data., , , , , , , and . SC Companion, page 1521-1522. IEEE Computer Society, (2012)